(1) Field of the Invention
The present invention relates to a non-volatile memory, and more particularly to a non-volatile memory device equipped with a means to electrically erase data of a memory cell.
(2) Description of the Related Art
First, a memory cell used in a conventional non-volatile memory of the kind to which the present invention relates is explained. FIG. 1 is a sectional view showing a memory cell structure in which data can be erased electrically. The structure and the basic write and erase operation of the memory cell are now explained.
A drain 102 and a source 103 of an N-type diffusion layer are formed within a surface region of a P-type semiconductor substrate 101. A tunnel oxide film 104 is formed on the P-type semiconductor substrate 101 and a floating gate 105 is formed on the tunnel oxide film 104. Further, an oxide film 106 is formed on the floating gate 105 and a control gate 107 is formed on the oxide film 106. This memory cell is a field effect transistor having a floating gate (hereinafter referred to as a "memory cell transistor").
There are two types of writing in the memory cell transistor. One is a channel hot electron injection type in which a high voltage is applied between the control gate 107 and the drain 102 with the source 103 being grounded and a hot electron generated by the flowing of a channel current is injected into the floating gate 105 through the tunnel oxide film 104. The other is a tunnel writing type in which a high voltage is applied to the control gate 107 with the drain 102 being open and the source 103 being grounded and, due to the tunnel effect between the floating gate 105 and the source 103, the electron is injected from the source 103 to the floating gate 105. The channel hot electron injection type is usually used for the writing in a unit of byte and the tunnel writing type is used for the writing of total bits at once. By this writing, the threshold voltage of the memory cell transistor rises to about 6 V from the erased state of 2 V.
For the erasing, the control gate 107 is grounded or set to a predetermined positive voltage with the drain 102 being open and the source receiving a high voltage and, due to the tunnel effect between the floating gate 105 and the source 103, the electrons charged or accumulated at the floating gate 105 are drawn to the source 103. By this erasing, the threshold voltage of the memory cell transistor falls to about 2 V from the writing state of 6 V. After the erasing, it is possible for the threshold voltage of the memory cell transistor to become negative, that is, a depletion type, and be always in an ON state when a voltage higher than the ground potential is applied to the control gate 107. This is called "excess erasing". Further, where the threshold voltage of the memory cell transistor after the erasing is high, there arises a problem that no sufficient ON current can be obtained while, where such threshold voltage is low, there arises a problem that the OFF current exceeds the permissible range.
For the memory transistor of the kind explained above, normally the ultraviolet light erasing is carried out, for example, during the last step of the diffusion process, and the threshold voltage of the memory transistor after the ultraviolet light erasing is determined by its oxide film thickness, its channel impurity concentration, etc. FIG. 2 shows in a graph the relation between the threshold voltages after the ultraviolet light erasing and the threshold voltages after the above explained electrical erasing that is obtained at each of the control gate voltages (Vcg) during the electrical erasing. It can be appreciated from FIG. 2 that the threshold voltage after the electrical erasing is higher as the threshold voltage of the memory cell transistor after the ultraviolet light erasing is higher and also as the control gate voltage Vcg during the erasing is higher. That is, where the control gate voltage Vcg is fixed, the threshold voltage after the electrical erasing varies depending on the variations in the thicknesses of the gate oxide film or the impurity concentrations of the channel of the memory transistor. For example, where, between chips or wafers, the threshold voltages of the memory transistor after the ultraviolet light erasing vary between 2 V and 4 V and, if the control gate voltage Vcg during the electrical erasing is 0 V, the threshold voltage of the memory transistor after the electrical erasing will have a variation of 2 V, that is, between 0 V and 2 V.
In order to solve the above problem, it is necessary to suppress the variations in the threshold voltages of the memory cell transistor after the electrical erasing. A method for this purpose is proposed in Japanese Patent Application Kokai Publication No. Hei-5 258583. According to the proposal, the excess erasing is made once until threshold voltage of the memory cell transistor in which the erasing rate is slowest becomes sufficiently low and, subsequently, the tunnel writing is carried out by applying the predetermined voltage to the control gate and injecting electrons to the floating gate of the memory cell transistor, and in this way the threshold voltage of the memory transistor is shifted to a positive direction and is made to converge to a predetermined fixed value. Here, by the tunnel writing, the threshold voltages of the memory cell transistor distributed at a lower voltage side are shifted to a positive direction so that, as shown by a dotted line in FIG. 2, the variation after the electrical erasing is suppressed to about 1 V even if the variation of the threshold voltage after the ultraviolet light erasing is between 2 V and 4 V.
Next, the configuration and the operation of the non-volatile memory having means to suppress the variation in the threshold voltage as explained above are explained. FIG. 3 is a circuit diagram showing an example of the conventional non-volatile memory of the related kind.
The non-volatile memory is composed of a memory cell array 1, a plurality of word lines WL1-WLm, a plurality of bit lines BL1-BLn, an X decoder 2, a Y decoder 3 and a bit line select circuit 4, a source voltage applying circuit 5, a write circuit 6, and a sense amplifier 7. In the memory cell array 1, a plurality of memory cell transistors MT11-MTmn each of which is a field effect transistor having a floating gate and constitutes a memory cell are arranged in a matrix form in row and column directions. Each of the word lines WL1-WLm is connected to a control gate of each memory cell transistor of the corresponding row provided in correspondence to each row of the memory cell transistors MT11-MTmn. Each of the bit lines BL1-BLn is connected to a drain of each memory cell transistor of the corresponding column provided in correspondence with each column of the memory cell transistors MT11-MTmn. The X decoder 2 controls the selection/non-selection and the potential of the word lines WL1-WLm in accordance with the operation mode control signal MCX and an X address signal ADX for controlling operation modes such as the read operation, write operation, and erase operation. The Y decoder 3 and the bit line select circuit 4 control the selection and connection between the bit lines BL1-BLm and the write circuit 6 and the sense amplifier 7 in accordance with the operation mode control signal and the Y address signal ADY. The source voltage applying circuit 5 applies an erase pulse (EP) of a predetermined pulse width and a predetermined voltage to a source (a source line SL) of one of the related memory transistors MT11-MTmn when the erase control signal ER is in an active level and renders the source line SL to a ground potential when in an inactive level. The write circuit 6 supplies a write voltage to the memory cell transistors MT11-MTmn through the bit line selection circuit 4. The sense amplifier 7 amplifies the read signal from the selected memory cell transistor.
The details of the X decoder 2 is shown in FIG. 4, in which each of the output circuit portions corresponding to the word lines WL1-WLm includes a NAND type logic gate G21, a CMOS inverter IV21 comprising a pair of transistors T21 and T22, a transistor T23 which controls by a first mode control signal MCX1 the connection between the inverter IV21 and a word line corresponding to this inverter IV21, and a transistor T24 which supplies the word line voltage Vwp in accordance with a second mode control signal MCX2.
Now, the erasing operation of the non-volatile memory of this embodiment is explained. The erasing of the memory is carried out by an excess erasing operation to cause the memory cell transistors MT11-MTmn to be in an excessively erased state and a tunnel write operation to reduce variations in the threshold voltages by compensating the excessively erased state. For the excess erasing operation, the Y select signals YS1-YSn are made low levels by the Y decoder 3 for the transistors T41-T4n to be turned off and the word lines WL1-WLm are made word line voltages Vwp in the order of 0 V or 1 V by the X decoder 2. Here, the word line voltage Vwp is supplied to the word lines WL1-WLm by turning off the transistor T23 and turning on the transistor T24 through the operation mode control signal MCX (MCX1, MCX2).
Then, in response to the active level of the erase control signal ER, an erase pulse EP of a high voltage having a predetermined width is outputted from the source voltage applying circuit 5 whereby the drains of the memory cell transistors MT11-MTmn change to an open state, the sources thereof change to a high voltage, and the control gates change to the word line voltage Vwp. Thus, the erasing is effected such that the memory cell transistor whose erase performance is the slowest results in an erased state.
Next, the tunnel write operation is explained. The Y select signals YS1-YSn are made low levels by the Y decoder 3 for the transistors T41-T4n to be turned off, and the word lines WL1-WLm are made a high voltage (by Vwp) on the order of 10 V by the X decoder 2. Further, the source line SL is made a ground potential level by the source voltage applying circuit 5 whereby the drains of the memory cell transistors MT11-MTmn change to an open state, the sources thereof change to a ground potential, and the control gates are made a high voltage, thus carrying out the tunnel write operation.
The erasing operation explained above enables the reduction of variations in the threshold voltages of the memory cell transistors MT11-MTmn after the erasing.
In the conventional non-volatile memory, in order to suppress the variations in the threshold voltages after the electrical erasing caused during the diffusion process by such variations as those in thicknesses of the gate oxide film and in channel impurity concentrations of the memory transistor, the erasing operation requires two steps, the first is to effect the preliminary excessive erasing and the second is to shift to the positive direction the threshold voltage of the memory cell transistor by the tunnel writing. A problem in this erasing operation is that, in addition to the complication in the operation, it requires time for the erasing. For example, in the case where the memory capacity is 32K bytes, the time required is about 0.1 seconds for the preliminary excessive erasing and about 0.5 seconds for the tunnel writing.